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1/63 december 2001 dsm2180f3v dsm (digital signal processor system memory) for analog devices adsp-218x family (3.3v supply) features summary n glueless connection to dsp C easily add memory, logic, and i/o to dsp n 128k byte flash memory C for bootloading and/or data overlay memory C programmable decoding and paging logic allows accessing flash memory as byte dma (bdma) and as external data overlay mem- ory C rapidly access flash memory with bdma for booting and loading internal dsp overlay memory. alternatively access the same flash memory as external data overlay memory to efficiently write flash memory with code up- dates and data, a byte at a time with no dma setup overhead C individual 16k byte flash memory sectors match size of dsp external data overlay window for efficient data management. inte- grated page logic provides easy dsp access to all 128k bytes. C dsm connects to lower byte of 16-bit dsp data bus. byte-wide accesses to 8-bit bdma space. half-word accesses to 16-bit data memory overlay and 16-bit i/o mem space. n 3 .3v devices (10%) n up to 16 multifunction i/o pins C increase total dsp system i/o capability C i/o controlled by dsp software or pld logic C 4ma i/o pin drive n general purpose pld C over 3,000 gates of pld with 16 macro cells C use for peripheral glue logic to keypads, con- trol panel, displays, lcd, uart devices, etc. C eliminate plds and external logic devices C create state machines, chip selects, simple shifters and counters, clock dividers, delays C simple psdsoft express tm software ...free figure 1. packages n in-system programming (isp) with jtag C program entire chip in 10-20 seconds with no involvement of the dsp C eliminate sockets for pre-programmed mem- ory and logic devices C efficient manufacturing allows easy product testing and just-in-time inventory C use low-cost flashlink tm cable with pc n content security C programmable security bit blocks access of device programmers and readers n zero-power technology C25 m a at v cc =3.3v n small packaging C 52-pin pqfp or 52-pin plcc n memory speed C150ns plcc52 (k) pqfp52 (t)
dsm2180f3v 2/63 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dsp address/data/control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 programmable logic (plds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 runtime control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 memory page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 jtag isp port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 security and nvm sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 specifying mem map with psdsoft expresstm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reading flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 erasing flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 flash memory sector protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dsm security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 reset flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 decode pld (dpld). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/63 dsm2180f3v dsp bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 port b C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 port c C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 port d C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pld power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 psd chip select input (csi, pd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power on reset, warm reset, power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 programming in-circuit using jtag isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table: absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table: operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table: dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table: cpld combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table: cpld macrocell synchronous clock mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: cpld macrocell asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table: read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table: write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table: flash memory program, write and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table: reset (reset) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table: isc timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table: plcc52 - 52 lead plastic leaded chip carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 57 table: assignments C plcc52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table: pqfp52 - 52 lead plastic quad flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table: pin assignments C pqfp52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table: ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
dsm2180f3v 4/63 summary description these are system memory devices for use with digital signal processors from the popular analog devices adsp-218x family. dsm means digital signal processor system memory. a dsm device brings in-system programmable flash memory, programmable logic, and additional i/o to dsp systems. the result is a simple and flexible two- chip solution for dsp designs. dsm devices pro- vide the flexibility of flash memory and smart jtag programming techniques for both manufac- turing and the field. on-chip integrated memory decode logic and memory paging logic make it easy to add large amounts of external flash mem- ory to the adsp-218x family for bootloading upon power-up and/or overlay memory. the dsp ac- cesses this flash memory using either its byte dma (bdma) interface or as external data overlay memory (no dma setup overhead). figure 2. plcc connections jtag in-system programming (isp) reduces de- velopment time, simplifies manufacturing flow, and lowers the cost of field upgrades. the jtag isp interface eliminates the need for sockets and pre-programmed memory and logic devices. for manufacturing, end products may be assembled with a blank dsm device soldered to the circuit board and programmed at the end of the manufac- turing line in 10 to 20 seconds with no involvement of the dsp. this allows efficient means to test product and manage inventory by rapidly pro- gramming test code, then application code as de- termined by inventory requirements (just-in time inventory). additionally, jtag isp reduces devel- opment time by turning fast iterations of dsp code in the lab. code updates in the field require no dis- assembly of product. the flashlink tm jtag pro- gramming cable costs $59 usd and plugs into any pc or note-book parallel port. figure 3. pqfp connections in addition to isp flash memory, dsm devices add programmable logic (pld) and up to 16 con- figurable i/o pins to the dsp system. the state of each i/o pin can be driven by dsp software or pld logic. pld and i/o configuration are program- mable by jtag isp, just like the flash memory. the pld consists of more than 3000 gates and has 16 macro cell registers. common uses for the pld include chip selects for external devices (i.e. uart), state-machines, simple shifters and counters, keypad and control panel interfaces, clock dividers, handshake delay, muxes, etc. this eliminates the need for small external plds and logic devices. configuration of pld, i/o, and flash memory mapping are easily entered in a point- and-click environment using the software develop- ment tool, psdsoft express tm . this software is available at no charge from www.psdst.com. pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 v cc ad7 ad6 ad5 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 47 48 49 50 51 52 1 2 3 4 5 6 7 ai02857 39 ad15 38 ad14 37 ad13 36 ad12 35 ad11 34 ad10 33 ad9 32 ad8 31 v cc 30 ad7 29 ad6 28 ad5 27 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntlo 14 15 16 17 18 19 20 21 22 23 24 25 26 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ai02858
5/63 dsm2180f3v figure 4. system block diagram, two-chip solution the two-chip combination of a dsp and a dsm device is ideal for systems which have limitations on size, emi levels, and power consumption. dsm memory and logic are zero-power, meaning they automatically go to standby between memory ac- cesses or logic input changes, producing low ac- tive and standby current consumption, which is ideal for battery powered products. ai04910 addr & decode logic flash memory 128k x 8 16 macrocell pld i/o control power management content security 8 i/o ports 8 i/o ports jtag isp to all areas i/o bus mem page control 22 address 8 data wr, rd, bms, dms, ioms i/o, pld, chip selects isp, i/o, pld, chip sel dsm2180f3 dsp system memory analog devices dsp adsp-218x family serial device serial device 13 flags / 4 intr
dsm2180f3v 6/63 a programmable security bit in the dsm protects its contents from unauthorized viewing and copy- ing. when set, the security bit will block access of programming devices (jtag or others) to the dsm flash memory and pld configuration. the only way to defeat the security bit is to erase the entire dsm device, after which the device is blank and may be used again. the dsp will always have access to flash memory contents through the 8-bit data port even while the security bit is set. table 1. dsm2180f3v dsp memory system devices table 2. compatible analog devices dsps part number isp flash memory flash partitioning pld i/o ports v cc and i/o mem speed dsm2180f3v-15 128k bytes eight 16k byte sectors 16 macro cells up to 16 3.3v 10% 150 ns dsp part numbers operating voltage, v cc i/o capability adsp-2183, 2184l, 2185l, 2186l, 2187l 3.3v 3.3v adsp-2185m, 2186m, 2188m, 2189m 2.5v 2.5 - 3.3v adsp-2185n, 2186n, 2187n, 2188n, 2189n 1.8v 1.8 - 3.3v
7/63 dsm2180f3v architectural overview major functional blocks are shown in figure 5. dsp address/data/control interface these dsp signals attach directly to the dsm in- puts for a glueless connection. an 8-bit data con- nection is formed and all 22 dsp address lines can be decoded while the dsp operates in full memory mode. dsp memory strobes; bms , dms , and ioms are used for bdma, data, & i/o access respectively (no program memory access, pms ). flash memory the 1 mbit (128k x 8) flash memory is divided into eight equally-sized 16k byte sectors that are indi- vidually selectable through the decode pld. each flash memory sector can be located at any ad- dress as defined by the user with psdsoft ex- press. the flexibility of the decode pld and page register logic allow the dsp to access flash memory as byte dma (bdma) or as external data overlay memory across several memory pages. bdma transfers are good for initial bootloading and for loading internal overlay memory at runt- ime, but bdma is not efficient writing to flash memory because flash memory is unlocked, writ- ten, and status is checked one byte at a time, re- quiring an initialization of the bdma channel for each and every byte transfer. the dsm device al- lows the dsp to alternatively access flash memo- ry as data overlay memory (using dms instead of bms ). writing flash memory this way is faster and requires simpler code. note: during a dsp data access using the dms strobe, only the upper byte of a 16-bit dsp data word is used. dsm flash memory sector size of 16k bytes matches the dsp external data memory overlay window size of 16k locations (two 8k windows when dmovlay register is used, see analog de- vices adsp-218x data sheets). this alignment provides convenient data management. also, each 16k byte sector can be loaded with contents from different firmware or data files specified in psdsoft express tm . miscellaneous: the dsp can erase flash memory by individual sectors or the entire flash memory array may be erased at one time. the flash mem- ory automatically goes to standby between dsp read or write accesses to conserve power. maxi- mum access times include sector decoding time. maximum erase cycles is 100k and data retention is 15 years minimum. flash memory, as well as the entire dsm device may be programmed with the jtag isp interface with no dsp involvement.
dsm2180f3v 8/63 figure 5. block diagram programmable logic (plds) the dsm family contains two plds that may op- tionally run in turbo or non-turbo mode. plds op- erate faster (less propagation delay) while in turbo mode but consume more power than non- turbo mode. non-turbo mode allows the plds to automatically go to standby when no inputs are change to conserve power. the turbo mode set- ting is controlled at runtime by dsp software. decode pld (dpld). this is programmable log- ic used to select one of the eight individual flash memory segments or the group of control registers within the dsm device. the dpld can also option- ally drive external chip select signals on port d pins. dpld input signals include: dsp address and control signals, page register outputs, dsm port pins, cpld logic feedback. complex pld (cpld). this programmable logic is used to create both combinatorial and sequen- tial general purpose logic. the cpld contains 16 output macrocells (omcs) and 16 input macro- cells (imcs). psd macrocell registers are unique in that that have direct connection to the dsp data bus allowing them to be loaded and read directly by the dsp at runtime. this direct access is good for making small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly by the dsp with little overhead. dpld in- puts include dsp address and control signals, page register outputs, dsm port pins, and cpld feedback. omcs: the general structure of the cpld is simi- lar in nature to a 22v10 pld device with the famil- iar sum-of-products (and-or) construct. true and compliment versions of 64 input signals are available to a large and array. and array outputs feed into a multiple product-term or gate within each omc (up to 10 product-terms for each omc). logic output of the or gate can be passed on as combinatorial logic or combined with a flip- flop within in each omc to realize sequential logic. omcs can be used as a buried nodes with feed- back to the and array or omc output can be rout- ed to pins on port b or portc. imcs: inputs from pins on port b or port c are routed to imcs for conditioning (clocking or latch- ing) as they enter the chip, which is good for sam- pling and debouncing inputs. alternatively, imcs can pass port input signals directly to pld inputs ai04911 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 i/o port pc0 pc1 pc3 pc4 pc5 pc6 i/o port complex pld (cpld) 16 input micro<>cells 16 output micro<>cells a b a b a b a b a b a b a b a b b c b c b c b c b c b c b c b c page reg security lock pld input bus allo- cator flash memory pin feedback node feedback dsm2180f3 dsp system memory internal addr, data, control bus linked to dsp decode pld (dpld) and array external chip selects fs0-7 jtag-isp to all areas of chip b b b b c c c c b c b c b c b c ad0 dsp addr ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 pc2 pc7 dsp control cntl0 cntl1 cntl2 rst\ pd0 pd1 pd2 3 optional outputs to port d pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 dsp data 8 segments, 16 kb 128 kbytes total runtime control csiop register file csiop power management fs0 fs7 fs6 fs5 fs4 fs3 fs2 fs1 external chip selects, esc0-2
9/63 dsm2180f3v without clocking or latching. the dsp may read the imcs at any time. runtime control registers a block of 256 bytes is decoded inside the dsm device as dsm control and status registers. 27 registers are used in the block of 256 locations to control the output state of i/o pins, to read i/o pins, to control power management, to read/write macrocells, and other functions at runtime. see table 4 for description. the base address of these 256 locations is referred to in this data sheet as csiop (chip select i/o port). individual registers within this block are accessed with an offset from the base address. the dsp accesses csiop regis- ters using i/o memory with the ioms strobe. csiop registers are accessed as bytes, so only the lower half of a dsp i/o word is used during access. memory page register this 8-bit register can be loaded and read by the dsp at runtime as one of the csiop registers. its outputs feed directly into the plds. the page reg- ister is a powerful feature that allows the dsp to access all 128k bytes of dsm flash memory in 16k byte pages. this size matches the 16k loca- tion data overlay window the adsp-218x family. page register outputs may also be used as cpld inputs for general use. i/o ports the dsm has 19 individually configurable i/o pins distributed over the three ports (ports b, c, and d). each i/o pin can be individually configured for dif- ferent functions such as standard mcu i/o ports or pld i/o on a pin by pin basis. (mcu i/o means that for each pin, its output state can be controlled or its input value can be read by the dsp at runt- ime using the csiop registers like an mcu would do.) port c hosts the jtag isp signals. since jtag- isp does not occur frequently during the life of a product, those port c pins are under-utilized. in applications that need every i/o pin, jtag signals can be multiplexed with general i/o signals to use them for i/o when not performing isp. see section titled programming in-circuit using jtag isp on page 41 for muxing jtag pins on port c, and ap- plication note an1153 . the static configuration of all port pins is defined with the psdsoft express tm software develop- ment tool. the dynamic action of the ports pins is controlled by dsp runtime software. jtag isp port in-system programming (isp) can be performed through the jtag signals on port c. this serial in- terface allows programming of the entire dsm device or subsections (that is, only flash memory but not the plds) without the participation of the dsp. a blank dsm device soldered to a circuit board can be completely programmed in 10 to 20 seconds. the basic jtag signals; tms, tck, tdi, and tdo form the ieee- 1149.1 interface. the dsm device does not implement the ieee- 1149.1 boundary scan functions. the dsm uses the jtag interface for isp only. however, the dsm device can reside in a standard jtag chain with other jtag devices and it will remain in by- pass m ode while other devices perform bound- ary scan. isp programming time can be reduced as much as 30% by using two more signals on port c, tstat and terr in addition to tms, tck, tdi and tdo. the flashlink tm jtag programming cable is available from stmicroelectronics for $59usd and psdsoft express software is available at no charge from www.psdst.com. that is all that is needed to program a dsm device using the paral- lel port on any pc or note-book. see section titled programming in-circuit using jtag isp on page 41. power management the dsm has bits in csiop control registers that are configured at run-time by the dsp to reduce power consumption of the cpld. the turbo bit in the pmmr0 register can be set to logic 1 and the cpld will go to non-turbo mode, meaning it will latch its outputs and go to sleep until the next tran- sition on its inputs. there is a slight penalty in pld performance (longer propagation delay), but sig- nificant power savings are realized. additionally, bits in two csiop registers can be set by the dsp to selectively block signals from enter- ing the cpld which reduces power consumption. see section titled power management on page 39. security and nvm sector protection a programmable security bit in the dsm protects its contents from unauthorized viewing and copy- ing. when set, the security bit will block access of programming devices (jtag or others) to the dsm flash memory and pld configuration. the only way to defeat the security bit is to erase the entire dsm device, after which the device is blank and may be used again. additionally, the contents of each individual flash memory sector can be write protected (sector pro- tection) by configuration with psdsoft express tm . this is typically used to protect dsp boot code from being corrupted by inadvertent writes to flash memory from the dsp. pin assignments pin assignment are shown for the 52-pin plcc package in figure 2, and the 52-pin pqfp pack- age in figure 3.
dsm2180f3v 10/63 table 3. pin description pin name type description adio0-15 in sixteen address inputs from the dsp. cntl0 in active low write strobe input (wr ) from the dsp cntl1 in active low read strobe input (rd ) from the dsp. cntl2 in active low byte memory select (bms ) signal from the dsp. reset in active low reset input from system. resets dsm i/o ports, page register contents, and other dsm configuration registers. must be logic low at power-up. pa0-7 i/o eight data bus signals connected to dsp pins d8 - d15. pb0-7 i/o eight configurable port b signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. cpld output macrocell (mcellab0-7 or mcellbc0-7) outputs. 3. inputs to the plds (input macrocells). note: each of the four port b signals pb0-pb3 may be configured at run-time as either standard cmos or for high slew rate. each of the four port b signals pb3-pb7 may be configured at run-time as either standard cmos or open drain outputs. pc0-7 i/o eight configurable port c signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. cpld output macrocell (mcellbc0-7) output. 3. input to the plds (input macrocells). 4. pins pc0, pc1, pc5, and pc6 can optionally form the jtag ieee-1149.1 isp serial interface as signals tms, tck, tdi, and tdo respectively. 5. pins pc3 and pc4 can optionally form the enhanced jtag signals tstat and terr respectively. reduces isp programming time by up to 30% when used in addition to the standard four jtag signals: tdi, tdo, tms, tck. 6. pin pc3 can optionally be configured as the ready/busy output to indicate flash memory programming status during parallel programming. may be polled by dsp or used as dsp interrupt to indicate when flash memory byte programming or erase operations are complete. note 1: port c pin pc2 input (or any pld input pin) can be connected to dsp d18 output which functions as dsp address a16 in dsp full memory mode. see figure 6. note 2: port c pin pc7 input (or any pld input pin) can be connected to dsp d19 output which functions as dsp address a17 in dsp full memory mode. see figure 6. note 3: when used as general i/o, each of the eight port c signals may be configured at run-time as either standard cmos or open drain outputs. note 4: the jtag isp pins may be multiplexed with other i/o functions. pd0-2 i/o three configurable port d signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. input to the plds (no associated input macrocells, routes directly into plds). 3. cpld output (external chip select). does not consume output macrocells. 4. pin pd1 can optionally be configured as clkin, a common clock input to pld. 5. pin pd2 can optionally be configured as csi , an active low chip select input to select flash memory. flash memory is disabled to conserve more power when csi is logic high. can connect csi to adsp-218x pwdack output signal. note 1: it is recommended to connect port d pin pd0 input to dsp ioms output which is the active low i/o memory select strobe. see figure 6. note 2: it is recommended to connect port d pin pd1 input to dsp dms output which is the active low data memory select strobe. see figure 6. note 3: it is recommended to connect port d pin pd2 input to dsp pwdack output if the dsp power down mode is used. see figure 6. v cc supply voltage gnd ground pins
11/63 dsm2180f3v typical connections figure 6 shows a typical connection scheme. many connection possibilities exist since most dsm pins are multipurpose. the scheme illustrat- ed is ideal for a design that needs fast jtag isp, eight additional general i/o with pld capability, access to flash memory as byte dma or as data overlay memory, and the dsp uses power down mode. if your design needs more i/o, or byte dma access to flash memory is all that is needed (no data overlay), or lowest power consumption is not an issue, then consider the following options. port c jtag: figure 6 shows all six jtag sig- nals in use full time (not multiplexed with i/0). us- ing six-pin jtag can reduce isp time by as much as 30% compared to four-pin jtag. alternatively, four-pin jtag (tms, tck, tdi, tdo) can be used if more general i/o pins are needed and the few extra seconds of programming time is not crucial, freeing up pins pc3 and pc4. other jtag options include mutiplexing jtag pins with general i/o (see programming in-circuit using jtag isp on page 41 and application note an1153 ) or not us- ing jtag at all. if no jtag is used, the dsm de- vice has to be programmed on a conventional programmer before it is installed on the circuit board. using no jtag makes more i/o available. pin pd1. if flash memory will be accessed only using byte dma mode in your design, and no ex- ternal data overlay memory accesses are used, then pin pd1 can be used for other purposes (mcui/o, common cpld clock input, external chip select, or pld input) pin pd2. if the dsp will not use power down mode, then pd2 can be used for other purposes (mcui/o, external chip select, pld input) pins pc2 and pc7. in figure 6, these two pins are used as dedicated address inputs connected to dsp address outputs. this will route dsp ad- dress signals a16 and a17 directly into the dpld. be aware that any free pin on port b, port c, or port d may be used for dsp address inputs, it does not have to be pins pc2 and pc7. pin pb0. this pin is shown as a chip select for an external peripheral device such as a 16450 or 16550 uart. equivalently, any free pin on ports b, c, or d may be used for this.
dsm2180f3v 12/63 figure 6. typical connections ai04912 adsp-218x a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 clkin xtal adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pc4 pc3 pc1 pc0 pc6 pc5 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 _reset a12 a13 d16 d17 adio12 adio13 adio14 adio15 addr12 addr13 addr14 addr15 d18 d19 pc2 pc7 addr16 addr17 chip sel pwdack pd2/_csi power down _reset _reset _reset jtag-isp connector tms tck t s tat _terr tdi tdo _reset gnd vcc sport0 serial chn serial device sport1 serial chn serial device fl0 fl1 fl2 _irql0/pf5 _irql1/pf6 pf3 _irq2/pf7 _irqe/pf4 pf0/modea pf1/modeb pf2/mocec i/o intr/i_o intr/i_o intr/i_o intr/i_o clock or xtal _br _bg _bgh bus_request grant_hung bus_grant pwr_down_in _pwd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o dsm2180f3 data8..15 data 8 data 9 data10 data11 data12 data13 data14 data15 d8 d9 d10 d11 d12 d13 d14 d15 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 byte mem select i/o mem select data mem select _rd _bms _ioms _dms pd1 cntl0 cntl1 cntl2 _wr pd0 write read write read addr0..2 _pms data optional parallel device (uart, etc) _rd _wr _select address n/c _cms n/c
13/63 dsm2180f3v memory map figure 7 shows a typical system memory map. the nomenclature fs0..fs7 are individual 16k byte flash memory segment designators. csiop desig- nates the dsm control register block. the dsp runs in full memory mode. memory contents of the dsm device may lie in one or more of three dif- ferent dsp address spaces; i/o space, byte dma space, and/or external data overlay memory space. since the dsm device is a byte-wide mem- ory, it typically is not used in dsp program mem- ory space ( pms active). the designer may easily specify memory mapping in a point-and-click software environment using psdsoft express tm . since the memory mapping is implemented with the dpld and the page regis- ter, many possibilities exist. figure 7 shows a typ- ical memory map with the following attributes: i/o address space. the 256 byte locations for dsm control registers ( csiop ) reside in dsp i/o address space, selected by the dsp ioms signal. since dsp i/o accesses are by 16 bits, not 8 bits, the upper byte of a 16-bit dsp i/o access must be ignored. byte dma address space. the dsp may boot- load or fetch overlay bytes from 128k bytes of flash memory using the dsp bdma channel. the dsp may also write to flash memory using the byte dma channel. dsm flash memory is access- ed in 128k continuous byte address locations through the bdma channel and is selected when- ever the dsp bms signal is active. flash memory in the dsm device must be un- locked and written by the dsp one byte at a time, checking status after each write (typical flash memory programming algorithm). a dma channel is not optimum for this scenario since the channel must be initialized on each byte access. that is why the 128k bytes of flash memory also lie in dsp data overlay memory space as described next. data overlay memory address space. all 128k bytes of flash memory also reside in dsp external data overlay memory space, selected by dms , allowing more efficient byte writes to flash memory. the dsp uses its external data overlay window of 8k locations to access external memory as data. the dsp doubles the size of this window to 16k locations by manipulating its a13 address line using its dmovlay register (see adsp-218x data sheets for details). since all 128k bytes of flash memory must be accessed through a win- dow of only 16k locations, the dsp uses the page register inside the dsm device to page through 8 pages of 16k bytes as shown in figure 7. since dsp data accesses are by 16 bits, not 8 bits, the upper byte of a 16-bit dsp data access must be ignored.
dsm2180f3v 14/63 figure 7. typical system memory map ai04913 04000 dsp byte dma memory space ( bms ) dsp data memory space ( dms ) 1ffff nothing mapped 07fff 08000 0bfff 0ffff 13fff 17fff 1bfff 1ffff 0c000 10000 14000 18000 1c000 03fff 00000 fs0 16 kbytes flash memory fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 16 kbytes (8 kwords) a13 = 1 a13 = 0 fs1 a13 = 1 a13 = 0 fs2 a13 = 1 a13 = 0 fs3 a13 = 1 a13 = 0 fs4 a13 = 1 a13 = 0 fs5 a13 = 1 a13 = 0 fs6 a13 = 1 a13 = 0 fs7 a13 = 1 a13 = 0 page 0 page 1 page 7 page 6 page 5 page 4 page 3 page 2 03fff 00000 03fff 00000 dsp i/o memory space ( ioms ) 00000 nothing mapped 1ffff csiop 256 control regs flash memory paged over 8 pages 000ff _cs_uart 8 uart regs 00200 00208 16 kbytes flash memory 16 kbytes flash memory 16 kbytes flash memory 16 kbytes flash memory 16 kbytes flash memory 16 kbytes flash memory 16 kbytes flash memory
15/63 dsm2180f3v specifying mem map with psdsoft express tm the memory map shown in figure 7 can be easily specified with psdsoft express tm in a point-and- click environment. psdsoft express tm will gener- ate hardware definition language (hdl) state- ments of the abel l anguage. figure 8 shows the resulting equations generated by psdsoft ex- press tm . figure 8. hdl statements generated from psdsoft express to implement memory map specifying these equations using psdsoft ex- press tm is very simple. figure 9 shows how to specify the equation for the 16k byte flash mem- ory segment, fs2 . notice how fs2 can reside in two different address spaces depending on the state of the control signals from the dsp ( ioms , dms , or bms ) and the memory page number coming from the dsm page register outputs. this specification process is repeated for all other flash memory segments, the csiop register block, and any exter- nal chip select signals (uart, etc.). csiop = ((address >= ^h0000) & (address <= ^h00ff) & (!_ioms & _dms & _bms)); fs0 = ((address >= ^h0000) & (address <= ^h3fff) & (_ioms & _dms & !_bms)) # ((page == 0) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs1 = ((address >= ^h4000) & (address <= ^h7fff) & (_ioms & _dms & !_bms)) # ((page == 1) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs2 = ((address >= ^h8000) & (address <= ^hbfff) & (_ioms & _dms & !_bms)) # ((page == 2) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs3 = ((address >= ^hc000) & (address <= ^hffff) & (_ioms & _dms & !_bms)) # ((page == 3) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs4 = ((address >= ^h10000) & (address <= ^h13fff) & (_ioms & _dms & !_bms)) # ((page == 4) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs5 = ((address >= ^h14000) & (address <= ^h17fff) & (_ioms & _dms & !_bms)) # ((page == 5) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs6 = ((address >= ^h18000) & (address <= ^h1bfff) & (_ioms & _dms & !_bms)) # ((page == 6) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); fs7 = ((address >= ^h1c000) & (address <= ^h1ffff) & (_ioms & _dms & !_bms)) # ((page == 7) & (address >= ^h0000) & (address <= ^h3fff) & (_ioms & !_dms & _bms)); ! _cs_uart = ((address >= ^h0200) & (address <= ^h0207) & (!_ioms & _dms & _bms));
dsm2180f3v 16/63 figure 9. psdsoft express tm memory mapping ai03779
17/63 dsm2180f3v runtime control register definition there are up to 256 addresses decoded inside the dsm device for control and status information. 27 of these locations contain registers that the dsp can access at runtime. the base address of this block of 256 locations is referred to in this manual as csiop (chip select i/o port). table 4 lists the 27 registers and their offsets (in hex) from the csiop base address needed to access individual dsm control and status registers. the dsp will access these registers in i/o memory space using its ioms strobe. these registers are accesses in bytes, so the dsp should ignore the upper byte of its 16-bit i/o access. note1: all csiop registers are cleared to logic 0 at reset. note2: do not write to unused locations within the csiop block of 256 registers. they should remain logic zero. table 4. csiop registers and their offsets (in hex) register name port b port c port d other description data in 01 10 11 mcui/o input mode. read to obtain current logic level of port pins. no writes. data out 05 12 13 mcu i/o output mode. write to set logic level on port pins. read to check status. direction 07 14 15 mcu i/o mode. configures port pin as input or output. write to set direction of port pins. logic 1 = out, logic 0 = in. read to check status. drive select 09 16 17 write to configure port pins as either standard cmos or open drain on some pins, while selecting high slew rate on other pins. read to check status. input macrocells 0b 18 read to obtain state of imcs. no writes. enable out 0d 1a 1b read to obtain the status of the output enable logic on each i/o port driver. no writes. output macrocells ab 20 read to get logic state of output of omc bank ab. write to load registers of omc bank ab. output macrocells bc 21 read to get logic state of output of omc bank bc. write to load registers of omc bank bc. mask macrocells ab 22 write to set mask for loading omcs in bank ab. a logic 1 in a bit position will block reads/writes of the corresponding omc. a logic 0 will pass omc value. read to check status. mask macrocells bc 23 write to set mask for loading omcs in bank bc. a logic 1 in a bit position will block reads/writes of the corresponding omc. a logic 0 will pass omc value. read to check status. flash sector protect c0 read to determine flash sector protection setting. no writes. security bit c2 read to determine if dsm devices security bit is active. logic 1 = device secured. no writes. jtag enable c7 write to enable jtag pins (optional feature). read to check status. pmmr0 b0 power management register 0. write and read. pmmr2 b4 power management register 2. write and read. page e0 memory page register. write and read.
dsm2180f3v 18/63 detailed operation figure 5 shows major functional areas of the de- vice: n flash memory n plds (dpld, cpld, page register) n dsp bus interface (address, data, control) n i/o ports n runtime control registers n jtag isp interface the following describes these functions in more detail. flash memory the flash memory array is divided evenly into eight equal 16k byte sectors. each sector is se- lected by the dpld can be separately protected from program and erase cycles. this configuration is specified by using psdsoft express tm . memory sector select signals. the dpld gen- erates the select signals for all the internal memo- ry blocks (see figure 14). each of the eight sectors of the flash memory has a select signal ( fs0- fs7 ) which contains up to three product terms. having three product terms for each select signal allows a given sector to be mapped into multiple areas of system memory. ready/busy (pc3). this signal can be used to output the ready/ busy status of the device. the output on ready/ busy (pc3) is a 0 (busy) when flash memory is being written, or when flash memory is being erased. the output is a 1 (ready) when no write or erase cycle is in progress. this signal may be polled by the dsp or used as a dsp interrupt to indicate when an erase or program cy- cle is complete. memory operation. the flash memory is ac- cessed through the dsp address, data, and con- trol bus interface. the dsp can access flash memory as bdma mode or as external data memory overlay. but from the dsm perspective, it sees either type of access as a series of byte op- erations (reads and writes). if the dsp accesses the dsm in bdma mode, then the dsp bdma channel must be initialized and run for each byte (or block of bytes) read from flash memory or it must initialize the dma channel for each byte writ- ten to flash memory. alternatively, if the dsp ac- cesses the dsm in external data memory overlay mode, then the dsp must only ensure the psd page register and the dsp dmovlay register contains the correct value, then it performs a nor- mal data read or data write operation without the burden of initializing the bdma channel for each operation (upper byte of 16-bit word is ignored). dsps and mcus cannot write to flash memory as it would an sram device. flash memory must first be unlocked with a special sequence of byte write operations to invoke an internal algorithm, then a single data byte is written to the flash mem- ory array, then programming status is checked by a byte read operation or by checking the ready/ busy pin (pc3). table 5 lists all of the special in- struction sequences to program (write) data to the flash memory array, erase the array, and check for different types of status from the array. these instruction sequences are different combinations of individual byte write and byte read operations. once the flash memory array is programmed (written) and then it is in read array mode, the dsp will read from flash memory just as if would from any 8-bit rom or sram device.
19/63 dsm2180f3v table 5. instruction sequences 1,2,3,4 note: 1. all values are in hexadecimal, x = dont care 2. a desired internal flash memory sector select signal (fs0 - fs7) must be active for each write or read cycle. only one of fs0 - fs7 will be active at any given time depending on the address presented by the dsp and the memory mapping defined in psdsoft ex- press. fs0 - fs7 are active high logic internally. 3. dsp addresses a17 through a12 are dont care during the instruction sequence decoding. only address bits a11-a0 are used during flash memory instruction sequence decoding bus cycles. the individual sector select signal (fs0 - fs7) which is active d ur- ing the instruction sequences determines the complete address. 4. for write operations, addresses are latched on the falling edge of write strobe (wr , cntl0), data is latched on the rising edge of write strobe (wr , cntl0) 5. no unlock or instruction cycles are required when the device is in the read array mode. operation is like reading a rom devic e. 6. the reset flash instruction is required to return to the normal read array mode if the error flag (dq5) bit goes high, or aft er read- ing the flash identifier or after reading the sector protection status. 7. the dsp cannot invoke this instruction sequence while executing code from the same flash memory as that for which the instruc - tion sequence is intended. the dsp must fetch, for example, the code from the dsp sram when reading the flash memory iden- tifier or sector protection status. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. directing this command to any individual active flash memory segment (fs0 - fs7) will invoke the bulk erase of all eight flas h memory sectors. 10. dsp writes command sequece to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. the byte 30h must be addressed to one of the other flash memory segments (fs0 - fs7) for each additional segment (write 30h to any address within a desired sector). no more than 80us can elapse between subsequent additional sector erase commands. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protect status, when in the suspend sector erase mode. the suspend sector erase instruction sequence is valid only during a sector erase cycle. 12. the resume sector erase instruction sequence is valid only during the suspend sector erase mode. instruction sequence cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read memory contents 5 read byte from any valid flash memory addr read flash identifier 6,7 write aah to xx555h write 55h to xxaaah write 90h to xx555h read identifier with addr lines a6,a1,a0 = 0,0,1 read memory sector protection status 6,7,8 write aah to xx555h write 55h to xxaaah write 90h to xx555h read identifier with addr lines a6,a1,a0 = 0,1,0 program a flash byte write aah to xx555h write 55h to xxaaah write a0h to xx555h write (program) data to addr flash bulk erase 9 write aah to xx555h write 55h to xxaaah write 80h to xx555h write aah to xx555h write 55h to xxaaah write 10h to xx555h flash sector erase 10 write aah to xx555h write 55h to xxaaah write 80h to xx555h write aah to xx555h write 55h to xxaaah write 30h to another sector write 30h to another sector suspend sector erase 11 write b0h to address that activates any of fs0 - fs7 resume sector erase 12 write 30h to addr that activates any of fs0 - fs7 reset flash 6 write f0h to address that activates any of fs0 - fs7
dsm2180f3v 20/63 instruction sequences an instruction sequence consists of a sequence of specific write or read operations. each byte written to the device is received and sequentially decoded and not executed as a standard write operation to the memory array. the instruction sequence is ex- ecuted when the correct number of bytes are prop- erly received and the time between two consecutive bytes is shorter than the time-out pe- riod. some instruction sequences are structured to include read operations after the initial write oper- ations. the instruction sequence must be followed exact- ly. any invalid combination of instruction bytes or time-out between two consecutive bytes while ad- dressing flash memory resets the device logic into read array mode (flash memory is read like a rom device). the device supports the instruction sequences summarized in table 5: flash memory: n erase memory by chip or sector n suspend or resume sector erase n program a byte n reset to read array mode n read primary flash identifier value n read sector protection status these instruction sequences are detailed in table 5. for efficient decoding of the instruction se- quences, the first two bytes of an instruction se- quence are the coded cycles and are followed by an instruction byte or confirmation byte. the coded cycles consist of writing the data aah to address xx555h during the first cycle and data 55h to ad- dress xxaaah during the second cycle. address signals a17-a12 are dont care during the instruc- tion sequence write cycles. however, the appro- priate internal sector select ( fs0-fs7 ) must be selected internally (active, which is logic 1). reading flash memory under typical conditions, the dsp may read the flash memory using read operations just as it would a rom or ram device. alternately, the dsp may use read operations to obtain status informa- tion about a program or erase cycle that is cur- rently in progress. lastly, the dsp may use instruction sequences to read special data from these memory blocks. the following sections de- scribe these read instruction sequences. read memory contents. flash memory is placed in the read array mode after power-up, chip reset, or a reset flash memory instruction sequence (see table 5). the dsp can read the memory contents of the flash memory by using read operations any time the read operation is not part of an instruction sequence. read flash identifier. the flash memory identi- fier is read with an instruction sequence composed of 4 operations: 3 specific write operations and a read operation (see table 5). during the read op- eration, address bits a6, a1, and a0 must be 0,0,1, respectively, and the appropriate internal sector select ( fs0-fs7 ) must be active. the iden- tifier 0xe3. read memory sector protection status. the flash memory sector protection status is read with an instruction sequence composed of 4 oper- ations: 3 specific write operations and a read oper- ation (see table 5). during the read operation, address bits a6, a1, and a0 must be 0,1,0, re- spectively, while internal sector select (fs0-fs7) designates the flash memory sector whose pro- tection has to be verified. the read operation pro- duces 01h if the flash memory sector is protected, or 00h if the sector is not protected. the sector protection status can also be read by the dsp accessing the flash memory protection register in csiop space. see the section entitled flash memory sector protect for register defini- tions. table 6. status bit definition note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. reading the erase/program status bits. the device provides several status bits to be used by the dsp to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the dsp spends performing these tasks and are defined in table 6. the status bits can be read as many times as needed. for flash memory, the dsp can perform a read operation to obtain these status bits while an erase or program instruction sequence is being executed by the embedded algorithm. see the functional block fs0-fs7 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash memory active (the desired segment is selected) data polling toggle flag error flag x erase time- out xxx
21/63 dsm2180f3v section entitled programming flash memory, on page 21, for details. data polling flag (dq7). when erasing or pro- gramming in flash memory, the data polling flag (dq7) bit outputs the complement of the bit being entered for programming/writing on the data poll- ing flag (dq7) bit. once the program instruction sequence or the write operation is completed, the true logic value is read on the data polling flag (dq7) bit (in a read operation). flash memory instruction features: n data polling is effective after the fourth write pulse (for a program instruction sequence) or after the sixth write pulse (for an erase instruction sequence). it must be performed at the address being programmed or at an address within the flash memory sector being erased. n during an erase cycle, the data polling flag (dq7) bit outputs a 0. after completion of the cycle, the data polling flag (dq7) bit outputs the last bit programmed (it is a 1 after erasing). n if the byte to be programmed is in a protected flash memory sector, the instruction sequence is ignored. n if all the flash memory sectors to be erased are protected, the data polling flag (dq7) bit is reset to 0 for about 100 s, and then returns to the previous addressed byte. no erasure is performed. toggle flag (dq6). the device offers another way for determining when the flash memory pro- gram cycle is completed. during the internal write operation and when the sector select fs0-fs7 is true, the toggle flag (dq6) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling stops and the data read on the data bus d0-7 is the addressed memory byte. the device is now accessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. flash memory specific fea- tures: n the toggle flag (dq6) bit is effective after the fourth write operation (for a program instruction sequence) or after the sixth write operation (for an erase instruction sequence). n if the byte to be programmed belongs to a protected flash memory sector, the instruction sequence is ignored. n if all the flash memory sectors selected for erasure are protected, the toggle flag (dq6) bit toggles to 0 for about 100 s and then returns to the previous addressed byte. error flag (dq5). during a normal program or erase cycle, the error flag (dq5) bit is to 0. this bit is set to 1 when there is a failure during flash memory byte program, sector erase, or bulk erase cycle. in the case of flash memory programming, the er- ror flag (dq5) bit indicates the attempt to program a flash memory bit from the programmed state, 0, to the erased state, 1, which is not valid. the error flag (dq5) bit may also indicate a time-out condi- tion while attempting to program a byte. in case of an error in a flash memory sector erase or byte program cycle, the flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. other flash memory sectors may still be used. the error flag (dq5) bit is reset after a reset flash instruction sequence. erase time-out flag (dq3). the erase time- out flag (dq3) bit reflects the time-out period al- lowed between two consecutive sector erase in- struction sequence bytes. the erase time-out flag (dq3) bit is reset to 0 after a sector erase cy- cle for a time period of 100 s + 20% unless an ad- ditional sector erase instruction sequence is decoded. after this time period, or when the addi- tional sector erase instruction sequence is decod- ed, the erase time-out flag (dq3) bit is set to 1. programming flash memory when a byte of flash memory is programmed, in- dividual bits are programmed to logic 0. you can- not program a bit in flash memory to a logic 1 once it has been programmed to a logic 0. a bit must be erased to logic 1, and programmed to log- ic 0. that means flash memory must be erased prior to being programmed. a byte of flash mem- ory is erased to all 1s (ffh). the dsp may erase the entire flash memory array all at once or indi- vidual sector-by-sector, but not byte-by-byte. however, the dsp may program flash memory byte-by-byte. the flash memory requires the dsp to send an in- struction sequence to program a byte or to erase sectors (see table 5). once the dsp issues a flash memory program or erase instruction sequence, it must check for the status bits for completion. the embedded algo- rithms that are invoked inside the device provide several ways give status to the dsp. status may be checked using any of three methods: data poll- ing, data toggle, or ready/busy (pin pc3). data polling. polling on the data polling flag (dq7) bit is a method of checking whether a pro-
dsm2180f3v 22/63 gram or erase cycle is in progress or has complet- ed. figure 10 shows the data polling algorithm. when the dsp issues a program instruction se- quence, the embedded algorithm within the device begins. the dsp then reads the location of the byte to be programmed in flash memory to check status. the data polling flag (dq7) bit of this lo- cation becomes the compliment of bit 7 of the orig- inal data byte to be programmed. the dsp continues to poll this location, comparing the data polling flag (dq7) bit and monitoring the error flag (dq5) bit. when the data polling flag (dq7) bit matches bit7 of the original data, and the error flag (dq5) bit remains 0, then the embedded al- gorithm is complete. if the error flag (dq5) bit is 1, the dsp should test the data polling flag (dq7) bit again since the data polling flag (dq7) bit may have changed simultaneously with the error flag (dq5) bit (see figure 10). the error flag (dq5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the dsp at- tempted to program a 1 to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the flash memory with the byte that was intended to be written. when using the data polling method during an erase cycle, figure 10 still applies. however, the data polling flag (dq7) bit is 0 until the erase cy- cle is complete. a 1 on the error flag (dq5) bit in- dicates a time-out condition on the erase cycle, a 0 indicates no error. the dsp can read any loca- tion within the sector being erased to get the data polling flag (dq7) bit and the error flag (dq5) bit. psdsoft express generates ansi c code func- tions which implement these data polling algo- rithms. figure 10. data polling flowchart data toggle. checking the toggle flag (dq6) bit is a method of determining whether a program or erase cycle is in progress or has completed. fig- ure 11 shows the data toggle algorithm. when the dsp issues a program instruction se- quence, the embedded algorithm within the device begins. the dsp then reads the location of the byte to be programmed in flash memory to check status. the toggle flag (dq6) bit of this location toggles each time the dsp reads this location until the embedded algorithm is complete. the dsp continues to read this location, checking the tog- gle flag (dq6) bit and monitoring the error flag (dq5) bit. when the toggle flag (dq6) bit stops toggling (two consecutive reads yield the same value), and the error flag (dq5) bit remains 0, then the embedded algorithm is complete. if the error flag (dq5) bit is 1, the dsp should test the toggle flag (dq6) bit again, since the toggle flag (dq6) bit may have changed simultaneously with the error flag (dq5) bit (see figure 11). read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
23/63 dsm2180f3v figure 11. data toggle flowchart the error flag (dq5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the dsp at- tempted to program a 1 to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to flash memory with the byte that was intended to be written. when using the data toggle method after an erase cycle, figure 11 st ill applies. the toggle flag (dq6) bit toggles until the erase cycle is com- plete. a 1 on the error flag (dq5) bit indicates a time-out condition on the erase cycle, a 0 indi- cates no error. the dsp can read any location within the sector being erased to get the toggle flag (dq6) bit and the error flag (dq5) bit. psdsoft express generates ansi c code func- tions which implement these data toggling algo- rithms. erasing flash memory flash bulk erase. the flash bulk erase instruc- tion sequence uses six write operations followed by a read operation of the status register, as de- scribed in table 5. if any byte of the bulk erase in- struction sequence is wrong, the bulk erase instruction sequence aborts and the device is re- set to the read flash memory status. the bulk erase command may be addresses to any one in- dividual valid flash memory segment ( fs0-fs7 ) and the entire array (all segments) will be erased. during a bulk erase, the memory status may be checked by reading the error flag (dq5) bit, the toggle flag (dq6) bit, and the data polling flag (dq7) bit, as detailed in the section entitled pro- gramming flash memory, on page 21. the error flag (dq5) bit returns a 1 if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the memory with 00h because the device automatically does this before erasing to 0ffh. during execution of the bulk erase instruction se- quence, the flash memory does not accept any in- struction sequences. the address provided with the flash bulk erase command sequence (table 5) may select any one of the eight internal flash memory sector select signals (fs0 - fs7). an erase of the entire flash memory array will occur even though the com- mand was sent to just one flash memory sector. flash sector erase. the sector erase instruc- tion sequence uses six write operations, as de- scribed in table 5. additional flash sector erase codes and flash memory sector addresses can be written subsequently to erase other flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100 s. the input of a new sector erase code restarts the time- out period. the status of the internal timer can be monitored through the level of the erase time-out flag (dq3) bit. if the erase time-out flag (dq3) bit is 0, the sector erase instruction sequence has been re- ceived and the time-out period is counting. if the erase time-out flag (dq3) bit is 1, the time-out period has expired and the device is busy erasing the flash memory sector(s). before and during erase time-out, any instruction sequence other than suspend sector erase and resume sector erase instruction sequences abort the cycle that is currently in progress, and reset the device to read array mode. it is not necessary to program the flash memory sector with 00h as the device does this automatically before erasing (byte=ffh). during a sector erase, the memory status may be checked by reading the error flag (dq5) bit, the toggle flag (dq6) bit, and the data polling flag (dq7) bit, as detailed in the section entitled pro- gramming flash memory, on page 21. during execution of the erase cycle, the flash memory accepts only reset and suspend sector erase instruction sequences. erasure of one read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle
dsm2180f3v 24/63 flash memory sector may be suspended, in order to read data from another flash memory sector, and then resumed. the address provided with the initial flash sector erase command sequence (table 5) must select the first desired sector (fs0 - fs7) to erase. sub- sequent sector erase commands that are append- ed on within the time-out period must be addressed to other desired segments (fs0 - fs7). suspend sector erase. when a sector erase cycle is in progress, the suspend sector erase in- struction sequence can be used to suspend the cycle by writing 0b0h to any address when an ap- propriate sector select (fs0-fs7) is selected (see table 5). this allows reading of data from an- other flash memory sector after the erase cycle has been suspended. suspend sector erase is accepted only during an erase cycle and defaults to read mode. a suspend sector erase instruc- tion sequence executed during an erase time-out period, in addition to suspending the erase cycle, terminates the time out period. the toggle flag (dq6) bit stops toggling when the device internal logic is suspended. the status of this bit must be monitored at an address within the flash memory sector being erased. the toggle flag (dq6) bit stops toggling between 0.1 s and 15 s after the suspend sector erase instruction sequence has been executed. the device is then automatically set to read mode. if an suspend sector erase instruction sequence was executed, the following rules apply: C attempting to read from a flash memory sector that was being erased outputs invalid data. C reading from a flash memory sector that was not being erased is valid. C the flash memory cannot be programmed, and only responds to resume sector erase and re- set flash instruction sequences (read is an op- eration and is allowed). C if a reset flash instruction sequence is re- ceived, data in the flash memory sector that was being erased is invalid. resume sector erase. if a suspend sector erase instruction sequence was previously exe- cuted, the erase cycle may be resumed with this instruction sequence. the resume sector erase instruction sequence consists of writing 030h to any address while an appropriate sector select (fs0-fs7) is active. (see table 5.) flash memory sector protect. each flash memory sector can be separately pro- tected against program and erase cycles. sector protection provides additional data security be- cause it disables all program or erase cycles. this mode can be activated through the jtag port or a device programmer. sector protection can be se- lected for each sector using psdsoft express. this automatically protects selected sectors when the device is programmed through the jtag port or a device programmer. flash memory sectors can be unprotected to allow updating of their con- tents using the jtag port or a device program- mer. the dsp can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash memory sector is ignored by the device. the verify operation results in a read of the protected data. this allows a guarantee of the retention of the pro- tection status. the sector protection status can be read by the dsp through the flash memory protection regis- ters (in the csiop block) as defined in table 7. table 7. sector protection/security bit definition C flash protection register note: 1. bit definitions: sec_prot 1 = flash memory sector is write protected. sec_prot 0 = flash memory sector is not write protected. table 8. security bit definition note: 1. bit definitions: 1 = security bit in device has been set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_bit not used not used not used not used not used not used not used
25/63 dsm2180f3v dsm security bit a programmable security bit in the dsm protects its contents from unauthorized viewing and copy- ing. when set, the security bit will block access of programming devices (jtag or others) to the dsm flash memory and pld configuration. the only way to defeat the security bit is to erase the entire dsm device, after which the device is blank and may be used again. the dsp will always have access to flash memory contents through the 8-bit data port even while the security bit is set. the dsp can read the status of the security bit (but it cannot change it) by reading the device security register in the csiop block as defined in table 8. reset flash the reset flash instruction sequence resets the internal memory logic state machine and puts flash memory into read array mode. it consists of one write cycle (see table 5). it must be executed after: C reading the flash protection status or flash id C an error condition has occurred (and the device has set the error flag (dq5) bit to 1) during a flash memory program or erase cycle. the reset flash instruction sequence puts the flash memory back into normal read array mode. it may take the flash memory up to a few millisec- onds to complete the reset cycle. the reset flash instruction sequence is ignored when it is is- sued during a program or bulk erase cycle of the flash memory. the reset flash instruction se- quence aborts any on-going sector erase cycle, and returns the flash memory to the normal read array mode within a few milliseconds. page register the 8-bit page register increases the addressing capability of the dsp by a factor of up to 256. the contents of the register can also be read by the dsp. the outputs of the page register (pg0- pg7) are inputs to the dpld decoder and can be included in the sector select ( fs0-fs7 ) equa- tions. see figure 12. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. the eight flip-flops in the register are con- nected to the internal data bus d0-d7. the dsp can write to or read from the page register. the page register can be accessed at address loca- tion csiop + e0h. page register outputs are cleared to logic 0 at reset. figure 12. page register plds the plds bring programmable logic to the device. after specifying the logic for the plds using psd- soft express, the logic is programmed into the de- vice and available upon power-up. the plds have selectable levels of performance and power consumption. the device contains two plds: the decode pld (dpld), and the complex pld (cpld), as shown in figure 13. table 9. dpld and cpld inputs note: 1. dsp address lines a16, a17, and others may enter the dsm device on any pin on ports b, c, or d. see figure 6 for recommended connections. 2. additional dsp control signals may enter the dms device on any pin on ports b, c, or d. see figure 6 for recom- mended connections. input source input name number of signals dsp address bus 1 a15-a0 16 dsp control signals 2 cntl2-cntl0 3 reset rst 1 portb input macrocells pb7-pb0 8 portc input macrocells pc7-pc0 8 port d inputs pd2-pd0 3 page register pg7-pg0 8 macrocell ab feedback mcellab fb7-0 8 macrocell bc feedback mcellbc fb7-0 8 flash memory program status bit ready/busy 1 reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal selects and logic pld pgr4 pgr5 pgr6 pgr7
dsm2180f3v 26/63 the dpld performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and i/o ports. the dpld can generates external chip select (ecs0-ecs2) signals on port d. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omc), 16 input macrocells (imc), and the and array. the and array is used to form product terms. these product terms are configured from the logic definition entered in psdsoft express. an input bus consisting of 64 signals is connected to the plds. input signals are shown in table 9. turbo bit. the plds in the device can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70 ns. resetting the turbo bit to 0 (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turning the turbo mode off increases propagation delays while reducing power consumption. additionally, five bits are available in the pmmr registers in csiop to block dsp control signals from entering the plds. this reduces power consumption and can be used only when these dsp control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. figure 13. pld diagram pld input bus 8 input macrocell and input ports direct macrocell input to mcu data bus csiop select decode pld (dpld) page register external chip selects to port d jtag select cpld pt alloc. macrocell alloc. mcellab mcellbc direct macrocell access from mcu data bus 16 input macrocell (port b,c) 16 output macrocell i/o ports flash memory selects 3 port d inputs to port b to port b or c data bus 8 8 8 1 3 1 64 16 64 16 output macrocell feedback ai04900b
27/63 dsm2180f3v decode pld (dpld) the dpld, shown in figure 14, is used for decod- ing the address for internal and external compo- nents. the dpld can be used to generate the following decode signals: n 8 flash memory sector select ( fs0-fs7 ) signals with three product terms each n 1 internal csiop select for dsm device control and status registers ( csiop is the base address of the block of 256 byte locations) n 1 jtag select signal (enables jtag operations on port c when multiplexing jtag signals with general i/o signals) n 3 external chip select output signals for port d pins, each with one product term. figure 14. dpld logic array (inputs) (16) (8) (16) (3) cntrl [ 2:0 ] ( read/write control signals) i /o ports (port a,b,c) (8) pg0 - pg7 (8) mcellab.fb [7:0] (feedback) mcellbc.fb [7:0] (feedback) a [ 15:0 ] (3) (1) pd [ 2:0 ] reset (1) rd_bsy csiop jtagsel ecs0 ecs1 8 flash memory sector selects i/o decoder select jtag isp fs0 fs7 3 3 3 3 3 3 3 3 1 ecs2 ai04901 fs1 fs2 fs3 fs6 fs5 fs4 1 1 1 1 external chip selects to port d
dsm2180f3v 28/63 complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. see application note an1171 for details on how to specify logic us- ing psdsoft express. as shown in figure 15, the cpld has the following blocks: n 16 input macrocells (imc) n 16 output macrocells (omc) n macrocell allocator n product term allocator n and array capable of generating up to 130 product terms n two i/o ports. each of the blocks are described in the sections that follow. the input macrocells (imc) and output macrocells (omc) are connected to the device internal data bus and can be directly accessed by the dsp. this enables the dsp software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and array as required in most standard pld macro cell architectures. figure 15. macrocell and i/o port output macrocell (omc). eight of the output macrocells (omc) are connected to port b pins and are named as mcellab0-mcellab7. the other eight macrocells are connected to ports b or c pins and are named as mcellbc0-mcellbc7. omcs may be used for internal feedback only (buried registers), or their outputs may be routed to external port pins. the output macrocell (omc) architecture is shown in figure 17. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other output macrocells (omc). the polarity of the product term is controlled by the xor gate. the output macrocell (omc) can im- plement either sequential logic, using the flip-flop i/o ports cpld macrocells input macrocells latched address out mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select macrocell to i/o port alloc. cpld output to other i/o ports pld input bus pld input bus dsp address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai04902b
29/63 dsm2180f3v element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the output macrocell (omc) block can be configured as a d, t, jk, or sr type in ps- dsoft express tm . the flip-flops clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, clkin (pd1) can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. output macrocell allocator. outputs of the 16 omcs can be routed to a combination of pins on port b or port d as shown in figure 16. the omc output pin is automatically determined by choosing pin functions in psdsoft express tm . routing can occur on a bit-by-bit basis, spitting assignment between the ports. however, one omc can be routed to one port pin only, not both. figure 16. omc allocator table 10. output macrocell port and data bit assignments product term allocator. the cpld has a prod- uct term allocator. psdsoft express tm uses the product term allocator to borrow and place prod- uct terms from one macrocell to another. this hap- pens automatically in psdsoft express tm , but understanding how allocation works will help you if your logic design does not fit, in which case you may try selecting a different pin or different omc where the allocation resources may differ and the design will then fit. the following list summarizes how product terms are allocated: n mcellab0-mcellab7 all have three native product terms and may borrow up to six more n mcellbc0-mcellbc3 all have four native product terms and may borrow up to five more n mcellbc4-mcellbc7 all have four native product terms and may borrow up to six more. ai04915 port c pins port b pins omcs (mcellbc) omcs (mcellab) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 4 5 6 7 3210 4 5 6 7 32 1 0 output macrocell port assignment native product terms maximum borrowed product terms data bit for loading or reading mcellab0 port b0 3 6 d0 mcellab1 port b1 3 6 d1 mcellab2 port b2 3 6 d2 mcellab3 port b3 3 6 d3 mcellab4 port b4 3 6 d4 mcellab5 port b5 3 6 d5 mcellab6 port b6 3 6 d6 mcellab7 port b7 3 6 d7 mcellbc0 port b0 or c0 4 5 d0 mcellbc1 port b1 or c1 4 5 d1 mcellbc2 port b or, c2 4 5 d2 mcellbc3 port b3 orc3 4 5 d3 mcellbc4 port b4 orc4 4 6 d4 mcellbc5 port b5 or c5 4 6 d5 mcellbc6 port b6 orc6 4 6 d6 mcellbc7 port b7 orc7 4 6 d7
dsm2180f3v 30/63 each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. product term allocation does not add any propagation delay to the logic. if an equation requires more product terms than are available to it through product term allocation, then external product terms are required, which consumes other output macrocells (omc). this is called product term expansion and also happens automatically in psdsoft express tm as needed. product tern expansion causes additional propa- gation delay because an omc is consumed by the expansion and its output is rerouted (or fed back) into the and array. you can examine the fitter report generated by psdsoft express to see resulting product term al- location and product term expansion. loading and reading the output macrocells (omcs). each of the two omc blocks (8 omcs each) occupies a memory location in the dsp ad- dress space, as defined in the csiop block mcellab0-7 and mcellbc0-7 (see table 4). the flip-flops in each of the 16 omcs can be load- ed from the data bus by a dsp. loading the omcs with data from the dsp takes priority over internal functions. as such, the preset, clear, and clock in- puts to the flip-flop can be overridden by the dsp. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and hand- shaking protocols. data is loaded into the output macrocells (omc) on the trailing edge of write strobe (wr , cntl0). figure 17. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin macrocell allocator internal data bus d [ 7:0 ] direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd output macrocell cs ai04903b
31/63 dsm2180f3v the omc mask register. there is one mask register for each of the two groups of eight output macrocells (omc). the mask registers can be used to block the loading of data to individual out- put macrocells (omc). the default value for the mask registers is 00h, which allows loading of the output macrocells (omc). when a given bit in a mask register is set to a 1, the dsp is blocked from writing to the associated output macrocells (omc). for example, suppose mcellab0-3 are be- ing used for a state machine. you would not want a dsp write to mcellab to overwrite the state ma- chine registers. therefore, you would want to load the mask register for mcellab (mask macrocell ab) with the value 0fh. the output enable of the omc. the output macrocells (omc) block can be connected to an i/ o port pin as a pld output. the output enable of each port pin driver is controlled by a single prod- uct term from the and array, ored with the direc- tion register output. the pin is enabled upon power-up if no output enable equation is defined and if the pin is declared as a pld output in psd- soft express. if the output macrocell (omc) output is specified as an internal node and not as a port pin output in the psdsoft express, then the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and ar- ray. figure 18. input macrocell input macrocells (imc). the cpld has 16 input macrocells (imc), one for each pin on ports b and c. the architecture of the imcs is shown in figure 18. the imcs are individually configurable, and can be used as a latch, a register, or to pass in- coming port signals prior to driving them onto the pld input bus. this is useful for sampling and de- bouncing inputs to the and array (keypad inputs, etc.). additionally, the outputs of the imcs can be read by the dsp asynchronously at any time through the internal data bus using the csiop reg- ister block (see table 4). the enable for the latch and clock for the register are driven by a product term from the cpld. each product term output is used to latch or clock four imcs. port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the imcs are specified by equa- tions specified in psdsoft express. see applica- tion note an1171 . output macrocells bc and macrocells ab pt pt feedback and array pld input bus port driver i/o pin internal data bus d [ 7: 0 ] direction register mux pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai04904b
dsm2180f3v 32/63 dsp bus interface the no-glue logic dsp bus interface allows di- rect connection. dsp address, data, and control signals connect directly to the dsm device. see figure 6 for typical connections. dsp address, data and control signals are routed to flash memory, i/o control ( csiop ), omcs, and imcs within the dms. the dsp address range for each of these components is specified in psdsoft express tm . i/o ports there are three programmable i/o ports: ports b, c, and d. each of the ports is eight bits except port d, which is 3 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft ex- press tm or by the dsp writing to on-chip registers in the csiop block. the topics discussed in this section are: n general port architecture n port operating modes n port configuration registers (pcr) n port data registers n individual port functionality. general port architecture. the general archi- tecture of the i/o port block is shown in figure 19. individual port architectures are shown in figure 20 to figure 23. in general, once the purpose for a port pin has been defined in psdsoft express tm , that pin is no longer available for other purposes. exceptions are noted. figure 19. general i/o port architecture as shown in figure 19, the ports contain an output multiplexer whose select signals are driven by the configuration bits determined by psdsoft express. inputs to the multiplexer include the following: n output data from the data out register (for mcu i/o mode) n cpld macrocell output (omc) n external chip selects esc0-2 from the dpld to port d pins only. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read by the dsp. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the dsp. the data out and macrocell out- internal data bus data out reg. dq dq wr wr macrocell outputs enable product term ( .oe ) ext cs read mux p d b cpld - input dir reg. input macrocell enable out data in output select output mux port pin data out ai04905b
33/63 dsm2180f3v puts, direction registers, and port pin input are all connected to the port data buffer (pdb). the port pins tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in psdsoft express tm , then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the dsp. the port data buffer (pdb) feedback path allows the dsp to check the contents of the registers. ports b, and c have embedded imcs. the imcs can be configured as registers (for sampling or de- bouncing), as transparent latches, or direct inputs to the plds. the registers and latches are clocked by a product term from the pld and array. the outputs from the imcs drive the pld input bus and can be read by the dsp. see the section entitled input macrocell, on page 31. port operating modes the i/o ports have several modes of operation. modes are defined using psdsoft express tm , and then runtime control from the dsp can occur using the registers in the csiop block. see application note an1171 for more detail. table 11 summarizes which modes are available on each port. each of the port operating modes are described in the following sections. table 11. port operating modes note: 1. can be multiplexed with other i/o functions. mcu i/o mode. in the mcu i/o mode, the dsp uses the i/o ports block to expand its own i/o ports. the dsp can read i/o pins, set the direction of i/o pins, and change the state of i/o pins by ac- cessing the registers in the csiop block. the csiop register definition and their addresses may be found in table 4. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the dsp can read the port input through the data in buffer. see figure 19. pld i/o mode. inputs from ports b and c to ei- ther pld (dpld or cpld) come through imcs. in- puts from port d to either plds are routed directly in and do not use imcs. outputs from the cpld to port b come from the omc group mcellab0-7. outputs from the cpld to port c come from omc group mcellbc0-7. outputs from the dpld to port d come from the external chip select logic block ecs0-2. all pld outputs may be tri-stated at the port pins with a control signal. this output enable control signal can be defined by a product term from the pld, or by resetting the corresponding bit in the direction register to 0. the corresponding bit in the direction register must not be set to logic 1 by the dsp if the pin is defined for a pld input signal in psdsoft express. the pld i/o mode is defined in psdsoft express by specifying pld equations. jtag in-system programming (isp). some of the pins on port c are based on the ieee 1194.1 jtag specification and is used for in-system pro- gramming (isp). you can multiplex the function of these port c jtag pins with other functions. isp is not performed very frequently in the life of the product, so multiplexing these pins functions with general purpose i/o functions gives more utility from port c. see the section entitled program- ming in-circuit using jtag isp, and application note an1153 . port configuration registers (pcr). each port has a set of port configuration registers (pcr) used for configuration of the pins. the contents of the registers can be accessed by the dsp through normal read/write bus cycles of the csiop registers listed in table 4. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port mode port b port c port d mcu i/o yes yes yes pld i/o mcellab outputs mcellbc outputs additional ext. cs outputs pld inputs ye s ye s no ye s no yes no yes no no ye s ye s jtag isp no ye s 1 no
dsm2180f3v 34/63 port. the three port configuration registers (pcr), are shown in table 12. default is logic 0. table 12. port configuration registers (pcr) note: 1. see table 16 for drive register bit definition. data in register. the dsp may read the data in registers in the csiop block at any time to deter- mine the logic state of a port pin. this will be the state at the pin regardless of whether it is driven by a source external to the dsm or driven internally from the dsm device. reading a logic zero for a bit in a data in register means the corresponding port pin is also at logic zero. reading logic one means the pin is logic one. each bit in a data in register corresponds to an individual port pin. for a given port, bit 0 in a data in register corresponds to pin 0 of the port. example, bit 0 of the data in register for port b corresponds to port b pin pb0. data out register. the dsp may write (or read) the data out register in the csiop block at any time. writing the data out register will change the logic state of a port pin only if it is not driven or controlled by the cpld. writing a logic zero to a bit in a data out register will force the corresponding port pin to be logic zero. writing logic one will drive the pin to logic one. each bit in the data out reg- isters correspond to port pins the same way as the data in registers described above. when some pins of a port are driven by the cpld, writing to the corresponding bit in a data out register will have no effect as the cpld overrides the data out register. direction register. the direction register, in conjunction with the output enable (except for port d), controls the direction of data flow in the i/o ports. any bit set to 1 in the direction register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. the default mode for all port pins is input. table 13. port pin direction control, output enable p.t. not defined table 14. port pin direction control, output enable p.t. defined table 15. port direction assignment example figure 20 and figure 21 show the port architec- ture diagrams for ports b and c, respectively. the direction of data flow for ports b, and c are con- trolled not only by the direction register, but also by the output enable product term from the pld and array. if the output enable product term is not ac- tive, the direction register has sole control of a given pins direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in table 15. since port d only contains three pins (shown in figure 23), the direction register for port d has only the three least significant bits active. drive select register. the drive select register configures the pin driver as open drain or cmos (standard push/pull) for some port pins, and con- trols the slew rate for the other port pins. an exter- nal pull-up resistor should be used for pins configured as open drain. open drain outputs are diode clamped, thus the maximum voltage on an pin configured as open drain is vcc + 0.7v. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a 1. the default pin drive is cmos. note that the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive reg- ister is set to 1. the default rate is standard slew. table 16 shows the drive register for ports b, c, and d. it summarizes which pins can be config- ured as open drain outputs and which pins the slew rate can be set for. register name port dsp access data in b,c,d read data out b,c,d write/read direction b,c,d write/read drive select 1 b,c,d write/read direction register bit port pin mode 0 input 1 output direction register bit output enable p. t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1
35/63 dsm2180f3v table 16. drive register pin assignment note: 1. na = not applicable. figure 20. port b structure port b C functionality and structure port b can be configured to perform one or more of the following functions: n mcu i/o mode n c pld output C macrocells mcellab7-mcellab0 can be connected to port b. mcellbc7- mcellbc0 can be connected to port b or port c. n cpld input C via the input macrocells (imc). n open drain/slew rate C pins pb3-pb0 can be configured to fast slew rate, pins pb7-pb4 can be configured to open drain mode. drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port b open drain open drain open drain open drain slew rate slew rate slew rate slew rate port c open drain open drain open drain open drain open drain open drain open drain open drain port d na 1 na 1 na 1 na 1 na 1 slew rate slew rate slew rate internal data bus data out reg. dq dq wr wr macrocell outputs enable product term ( .oe ) read mux p d b cpld - input dir reg. input macrocell enable out data in output select output mux port b pin data out ai04906b
dsm2180f3v 36/63 figure 21. port c structure port c C functionality and structure port c can be configured to perform one or more of the following functions (see figure 21): n mcu i/o mode n c pld output C mcellbc7-mcellbc0 outputs can be connected to port b or port c. n cpld input C via the input macrocells (imc) n in-system programming (isp) C jtag port can be enabled for programming/erase of the device. (see the section entitled programming in-circuit using jtag isp, and application note an1153 , for more information on jtag programming.) n open drain C port c pins can be configured in open drain mode internal data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term ( .oe ) read mux p d b cpld - input dir reg. input macrocell enable out jtag isp jtag isp configuration bit data in output select output mux port c pin data out ai04907
37/63 dsm2180f3v figure 22. port d structure port d C functionality and structure port d has three i/o pins. see figure 22 and fig- ure 23. port d can be configured to perform one or more of the following functions: n mcu i/o mode n d pld output C external chip selects, ecs0-2 does not consume omcs n cpld input C direct input to the cpld, does not use imcs n slew rate C pins can be set up for fast slew rate port d pins can be configured in psdsoft as in- put pins for other dedicated functions: n clkin (pd1) as input to the omcs flip-flops n psd chip select input (csi , pd2). driving this signal logic high disables the flash memory, putting it in standby mode. external chip select. the dpld also provides three external chip select outputs (esc0-2) on port d pins that can be used to select external de- vices as defined in psdsoft express. each exter- nal chip select consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 23.) external chip selects for port d pins do not consume omcs. external chip select outputs can also come from the cpld if chip se- lect equations are specified in psdsoft express for ports b or c. internal data bus data out reg. dq dq wr wr ecs [ 2: 0 ] read mux p d b cpld - input dir reg. data in enable product term (.oe) output select output mux port d pin data out ai02889
dsm2180f3v 38/63 figure 23. port d external chip select signals pld input bus polarity bit pd2 pin pt2 ecs2 direction register polarity bit pd1 pin pt1 ecs1 enable (.oe) enable (.oe) direction register polarity bit pd0 pin pt0 ecs0 enable (.oe) direction register cpld and array ai02890
39/63 dsm2180f3v power management the device offers configurable power saving op- tions. these options may be used individually or in combinations, as follows: n all memory blocks in the device are built with zero-power management technology. zero- power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory wakes up, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingit happens automatically. both plds (dpld and cpld) are also zero- power, but this is not the default operation. the dsp must set a bit at run-time to achieve zero- power as described next. n the pmmr registers can be written by the dsp at run-time to manage power. the device has a turbo bit in the pmmr0 register. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc current component and the ac component is higher. further significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. the blocking bits in pmmr registers can be set to logic 1 by the dsp to block designated signals from reach- ing both plds. current consumption of the plds is directly related to the composite fre- quency of the changes on their inputs (see fig- ure 25), so blocking unused pld inputs can significantly lower pld operating frequency and power consumption. the dsp also has the op- tion of blocking certain pld input when not needed, then letting them pass for when needed for specific logic operations. table 17 and table 18 define the pmmr registers. n psd chip select input (csi , pd2) can be used to disable the internal memories and csiop registers, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. there is a slight penalty in memory access time when psd chip select input (csi , pd2) makes its initial transition from deselected to selected. table 17. power management mode registers pmmr0 1 note: 1. the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 x 0 not used, and should be set to zero. bit 3 pld turbo 0 = on pld turbo mode is on 1 = off pld turbo mode is off, saving power. bit 4 pld array clk 0 = on clkin (pd1) input to the pld and array is passed onto plds. every change of clkin (pd1) powers-up the pld when turbo bit is 0. 1 = off clkin (pd1) input to pld and array is blocked, saving power. bit 5 pld mcell clk 0 = on clkin (pd1) input to the pld macrocells is passed onto plds. 1 = off clkin (pd1) input to pld macrocells is blocked, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero.
dsm2180f3v 40/63 pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to 1, the turbo mode is off and the plds consume the specified stand-by current when the inputs are not switching for an extended time of 100 ns. the propagation delay time is increased by 10 ns after the turbo bit is set to 1 (turned off) when the inputs change at a composite frequency of less than 10 mhz. when the turbo bit is reset to 0 (turned on), the plds run at full power and speed. the turbo bit affects the plds dc power, ac power, and propagation delay. blocking mcu control signals with the bits of the pmmr registers can further reduce pld ac power consumption by lowering the effective composite frequency of inputs to the plds. table 18. power management mode registers pmmr2 1 note: 1. the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. psd chip select input (csi , pd2) pd2 of port d can be configured in psdsoft ex- press as psd chip select input ( csi ). when low, the signal selects and enables the internal flash memory and i/o blocks for read or write opera- tions involving the device. a high on psd chip se- lect input ( csi , pd2) disables the flash memory and reduces the device power consumption. how- ever, the pld and i/o signals remain operational when psd chip select input ( csi , pd2) is high. there may be a timing penalty when using psd chip select input ( csi , pd2) depending on the speed grade of the device that you are using. see the timing parameter t slqv in table 31. input clock. the device provides the option to block clkin (pd1) from reaching the plds to save ac power consumption. clkin (pd1) is an input to the pld and array and the omcs. if clkin (pd1) is not being used as part of the pld logic equation, the clock should be blocked to save ac power. clkin (pd1) is disconnected from the pld and array or the macrocells block by setting bits 4 or 5 to a 1 in pmmr0. input control signals. the device provides the option to block the input control signals (cntl0, cntl1, cntl2, pd0, and pc7) from reaching the plds to save ac power consumption. these con- trol signals are inputs to the pld and array. if any of these are not being used as part of the pld log- ic equation, these control signals should be dis- abled to save ac power. they are disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a 1 in the pmmr2 register. note: cntl0 and cntl1 (dsp wr and dsp rd ) are perma- nently routed to the flash memory array and can- not be blocked from the array by the pmmr registers (thats why wr and rd signals do not have to be specified in psdsoft express for flash memory segment chip-select equations for fs0 - fs7). cntl0 and cntl1 are blocked from the plds with pmmr registers bits when these sig- nals are specifically used in logic equations speci- fied in psdsoft express. bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 pld array cntl0 0 = on cntl0 input to the pld and array is passed onto plds. 1 = off cntl0 input to pld and array is blocked, saving power. bit 3 pld array cntl1 0 = on cntl1 input to the pld and array is passed onto plds. 1 = off cntl1 input to pld and array is blocked, saving power. bit 4 pld array cntl2 0 = on cntl2 input to the pld and array is passed onto plds. 1 = off cntl2 input to pld and array is blocked, saving power. bit 5 pld array pd0 0 = on pd0 input to the pld and array is passed onto plds. 1 = off pd0 input to pld and array is blocked, saving power. bit 6 pld array pc7 0 = on pc7 input to the pld and array is passed onto plds. 1 = off pc7 input to pld and array is blocked, saving power. bit 7 x 0 not used, and should be set to zero.
41/63 dsm2180f3v figure 24. reset (reset ) timing power on reset, warm reset, power-down power on reset. upon power-up, the device re- quires a reset ( reset ) pulse of duration t nlnh-po after v cc is steady. during this time period, the de- vice loads internal configurations, clears some of the registers and sets the flash memory into op- erating mode. after the rising edge of reset ( re- set ), the device remains in the reset mode for an additional period, t opr , before the first memory ac- cess is allowed. the flash memory is reset to the read array mode upon power-up. sector select fs0-fs7 must all be low, write strobe ( wr , cntl0) high, during power on reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of write strobe ( wr , cntl0). any flash memory write cy- cle initiation is prevented automatically when v cc is below v lko . table 19. status during power-on reset, warm reset and power-down mode warm reset. once the device is up and running, the device can be reset with a pulse of a much shorter duration, t nlnh . the same t opr period is needed before the device is operational after warm reset. figure 24 shows the timing of the power-up and warm reset. i/o pin, register and pld status at reset. ta- ble 19 shows the i/o pin, register and pld status during power on reset, warm reset and power- down mode. pld outputs are always valid during warm reset, and they are valid in power on reset once the internal device configuration bits are loaded. this loading of the device is completed typically long before the v cc ramps up to operat- ing level. once the pld is active, the state of the outputs are determined by the psdsoft express equations. programming in-circuit using jtag isp in-system programming (isp) can be performed through the jtag signals on port c. this serial in- terface allows programming of the entire dsm de- vice or subsections (i.e. only flash memory but not the plds) without and participation of the dsp. a blank dsm device soldered to a circuit board can be completely programmed in 10 to 20 seconds. the basic jtag signals; tms, tck, tdi, and tdo form the ieee-1149.1 interface. the dsm device does not implement the ieee-1149.1 boundary scan functions. the dsm uses the jtag interface for isp only. however, the dsm device can reside in a standard jtag chain with other jtag devices as it will remain in bypass mode while other devices perform boundary scan. t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset port configuration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) register power-on reset warm reset power-down mode pmmr0 and pmmr2 cleared to 0 unchanged unchanged omc flip-flop status cleared to 0 by internal power-on reset depends on .re and .pr equations depends on .re and .pr equations all other registers cleared to 0 cleared to 0 unchanged
dsm2180f3v 42/63 isp programming time can be reduced as much as 30% by using two more signals on port c, tstat and terr in addition to tms, tck, tdi and tdo. see table 20. the flashlink tm jtag program- ming cable available from stmicroelectronics for $59usd and psdsoft express software that is available at no charge from www.psdst.com is all that is needed to program a dsm device using the parallel port on any pc or laptop. by default, the four pins on port c are enabled for the basic jtag signals tms, tck, tdi, and tdo on a blank device (and as shipped from factory) see application note an1153 for more details on jtag in-system programming (isp). standard jtag signals. the standard jtag signals (tms, tck, tdi, and tdo) can be en- abled by any of three different conditions that are logically ored. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a jtag serial command from an external jtag controller device (such as flashlink or automated test equip- ment). when the enabling command is received, tdo becomes an output and the jtag channel is fully functional inside the device. the same com- mand that enables the jtag channel may option- ally enable the two additional jtag signals, tstat and terr . the following symbolic logic equation specifies the conditions enabling the four basic jtag signals (tms, tck, tdi, and tdo) on their respective port c pins. for purposes of discussion, the logic label jtag_on is used. when jtag_on is true, the four pins are enabled for jtag operation. when jtag_on is false, the four pins can be used for general device i/o as specified in psd- soft express. jtag_on can become true by any of three different ways as shown: jtag_on = 1. psdsoft express pin configuration -or- 2. psdsoft express pld equation -or- 3. dsp writes to register in csiop block method 1 is most common. this is when the jtag pins are selected in psdsoft express to be dedi- cated jtag pins. they can always transmit and receive jtag information because they are full- time jtag pins. method 2 is used only when the jtag pins are multiplexed with general i/o functions. for de- signs that need every i/o pin, the jtag pins may be used for general i/o when they are not used for isp. however, when jtag pins are multiplexed with general i/o functions, the designer must in- clude a way to get the pins back into jtag mode when it is time for jtag operations again. in this case, a single pld input from ports b, c, or d must be dedicated to switch the port c pins from i/ o mode back to isp mode at any time. it is recom- mended to physically connect this dedicated pld input pin to the jen\ output signal from the flashlink cable when multiplexing jtag signals. see application note an1153 for details. method 3 is rarely used to control jtag pin oper- ation. the dsp can set the port c pins to function as jtag isp by setting the jtag enable bit in a register of the csiop block, but as soon as the dsm chip is reset, the csiop block registers are cleared, which turns off the jtag-isp function. controlling jtag pins using this method is not recommended. table 20. jtag port signals jtag extensions. tstat and terr are two jtag extension signals (must be used as a pair) enabled by a command received over the four standard jtag signals (tms, tck, tdi, and tdo) by psdsoft express. they are used to speed program and erase cycles by indicating status on device pins instead of having to scan the status out serially using the standard jtag chan- nel. see application note an1153 . terr indicates if an error has occurred when erasing a sector or programming a byte in flash memory. this signal goes low (active) when an error condition occurs. tstat behaves the same as ready/busy de- scribed previously. tstat is inactive logic 1 when the device is in read mode (flash memory con- tents can be read). tstat is logic 0 when flash memory program or erase cycles are in progress. tstat and terr can be configured as open- drain type signals with psdsoft express. this fa- cilitates a wired-or connection of tstat signals from multiple dsm2180f3v devices and a wired- or connection of terr signals from those same devices. this is useful when several devices are chained together in a jtag environment. psd- soft express puts tstat and terr signals to open-drain by default. click on 'properties' in the jtag-isp window of psdsoft express to change to standard cmos push-pull. it is recommended port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status pc4 terr error flag pc5 tdi serial data in pc6 tdo serial data out
43/63 dsm2180f3v to use 10 k w pull-up resistors to v cc on all jtag- isp signals on your circuit board. initial delivery state when delivered from st, the device has all bits in the memory and plds erased to logic 1. the dsm configuration register bits are set to 0. the code, configuration, and pld logic are loaded using the programming procedure. the four basic jtag isp signals (tck, tms, tdi, tdo) are ready for isp function.
dsm2180f3v 44/63 ac/dc parameters these tables describe the ad and dc parameters of the device: o dc electrical specification o ac timing specification n pld timing C combinatorial timing C synchronous clock mode C asynchronous clock mode C input macrocell timing n dsp timing C read timing Cwrite timing C reset timing the following are issues concerning the parame- ters presented: n in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the device is in each mode. also, the supply power is considerably different if the turbo bit is 0. n the ac power component gives the pld and flash memory a ma/mhz specification. figure 25 show the pld ma/mhz as a function of the number of product terms (pt) used. n in the pld timing parameters, add the required delay when turbo bit is 0. figure 25. pld i cc /frequency consumption 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc C (ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100
45/63 dsm2180f3v maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 21. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature C65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) C0.6 7.0 v v cc supply voltage C0.6 7.0 v v pp device programmer supply voltage C0.6 14.0 v v esd electrostatic discharge voltage (human body model) 2 C2000 2000 v
dsm2180f3v 46/63 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 22. operating conditions table 23. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 26. ac measurement i/o waveform figure 27. ac measurement load circuit table 24. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (industrial) C40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 1.5 v input and output timing reference voltages 1.5 v 0.9v cc 0v test point 1.5v ai04947 device under test 2.0 v 400 w c l = 30 pf (including scope and jig capacitance) ai04948 symbol parameter test condition typ . 2 max . unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf
47/63 dsm2180f3v table 25. ac symbols for pld timing example: t avwl C time from address valid to write input low. figure 28. switching waveforms C key signal letters signal behavior a address input t time c ceout output l logic level low d input data h logic level high e e input v valid n reset input or output x no longer a valid logic level p port signal output z float q output data pw pulse width rrd input (read) s chip select input, bms , dms , ioms , or fsx wwr input (write) b v stby output m output macrocell waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
dsm2180f3v 48/63 table 26. dc characteristics note: 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc C0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 25 for the pld current calculation. 5. i out = 0 ma symbol parameter conditions min. typ. max. unit v ih high level input voltage 3.0 v < v cc < 3.6 v 0.7v cc v cc +0.5 v v il low level input voltage 3.0 v < v cc < 3.6 v C0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) C0.5 0.2v cc C0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.5 2.2 v v ol output low voltage i ol = 20 a, v cc = 3.0v 0.01 0.1 v i ol = 4 ma, v cc = 3.0 v 0.15 0.45 v v oh output high voltage except v stby on i oh = C20 a, v cc = 3.0 v 2.9 2.99 v i oh = C2 ma, v cc = 3.0 v 2.7 2.6 v v oh1 output high voltage v stby on i oh1 = 1 a v stby C 0.8 v i idle idle current (vstby input) v cc > v stby C0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power-down mode csi >v cc C0.3 v (notes 2,3 ) 25 100 a i li input leakage current v ss < v in < v cc C1 .1 1 a i lo output leakage current 0.45 < v in < v cc C10 5 10 a i cc (dc) (note 5 ) operating supply current pld only pld_turbo = off, f = 0 mhz (note 3 ) 0 a/pt pld_turbo = on, f = 0 mhz 200 400 a/pt flash memory during flash memory write/ erase only 10 25 ma read only, f = 0 mhz 0 0 ma i cc (ac) (note 5 ) pld ac adder (see note 4 ) flash memory ac adder 1.5 2.0 ma/ mhz
49/63 dsm2180f3v table 27. cpld combinatorial timing note: 1. fast slew rate output available on pb3-pb0, and pd2-pd0. symbol parameter conditions -15 pt aloc turbo off slew rate 1 unit min max t pd cpld input pin/feedback to cpld combinatorial output 45 add 4 add 20 sub 6 ns t ea cpld input to cpld output enable 45 add 20 sub 6 ns t er cpld input to cpld output disable 45 add 20 sub 6 ns t arp cpld register clear or preset delay 43 add 20 sub 6 ns t arpw cpld register clear or preset pulse width 30 add 20 ns t ard cpld array delay any macrocell 29 add 4 ns
dsm2180f3v 50/63 table 28. cpld macrocell synchronous clock mode timing note: 1. fast slew rate output available on pb3-pb0, and pd2-pd0. 2. clkin (pd1) t clcl = t ch + t cl . table 29. cpld macrocell asynchronous clock mode timing symbol parameter conditions -15 pt aloc turbo off slew rate 1 unit min max f max maximum frequency external feedback 1/(t s +t co ) 18.8 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co C10) 23.2 mhz maximum frequency pipelined data 1/(t ch +t cl ) 33.3 mhz t s input setup time 25 add 4 add 20 ns t h input hold time 0 ns t ch clock high time clock input 15 ns t cl clock low time clock input 15 ns t co clock to output delay clock input 28 sub 6 ns t ard cpld array delay any macrocell 29 add 4 ns t min minimum clock period 2 t ch +t cl 29 ns symbol parameter conditions -15 pt aloc turbo off slew rate unit min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 19.2 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa C10) 23.8 mhz maximum frequency pipelined data 1/(t cha +t cla ) 27 mhz t sa input setup time 12 add 4 add 20 ns t ha input hold time 15 ns t cha clock high time 22 add 20 ns t cla clock low time 15 add 20 ns t coa clock to output delay 40 add 20 sub 6 ns t ard cpld array delay any macrocell 29 add 4 ns t mina minimum clock period 1/f cnta 42 ns
51/63 dsm2180f3v figure 29. input to output disable / enable figure 30. asynchronous reset / preset figure 31. synchronous clock mode timing C pld figure 32. asynchronous clock mode timing (product term clock) ter tea input input to output enable/disable ai02863 tarp register output tarpw reset/preset input ai02864 t ch t cl t co t h t s clkin input registered output ai02860 tcha tcla tcoa tha tsa clock input registered output ai02859
dsm2180f3v 52/63 table 30. input macrocell timing note: 1. inputs from port b, and c relative to register/latch clock from the pld. figure 33. input macrocell timing (product term clock) symbol parameter conditions -15 pt aloc turbo off unit min max t is input setup time (note 1 ) 0ns t ih input hold time (note 1 ) 25 add 20 ns t inh nib input high time (note 1 ) 13 ns t inl nib input low time (note 1 ) 13 ns t ino nib input to combinatorial delay (note 1 ) 62 add 4 add 20 ns t inh t inl t ino t ih t is pt clock input output ai03101
53/63 dsm2180f3v table 31. read timing note: 1. any input used to select an internal dsm function. figure 34. read timing symbol parameter conditions -15 turbo off unit min max t avqv address valid to data valid (note 1 ) 150 add 20 ns t slqv cs valid to data valid 150 ns t rlqv rd to data valid 8-bit bus 35 ns t rhqx rd data hold time 1 ns t rlrh rd pulse width 40 ns t rhqz rd to data high-z 20 ns t avqv t slqv t rlqv t rhqx trhqz t rlrh address valid data valid address non-multiplexed bus data non-multiplexed bus csi rd ai04908
dsm2180f3v 54/63 table 32. write timing note: 1. any input used to select an internal psm function. 2. assuming data is stable before active write signal. 3. assuming write is active before data becomes valid. 4. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal dsm memory. figure 35. write timing symbol parameter conditions -15 unit min max t avwl address valid to leading edge of wr (notes 1 ) 0ns t slwl cs valid to leading edge of wr 0ns t dvwh wr data setup time 45 ns t whdx wr data hold time 2 ns t wlwh wr pulse width 48 ns t whax1 trailing edge of wr to address invalid 1.75 ns t whax2 trailing edge of wr to dpld address invalid (note 4 ) 0ns t whpv trailing edge of wr to port output valid using i/o port data register 35 ns t dvmv data valid to port output valid using macrocell register preset/clear (note 3 ) 70 ns t wlmv wr valid to port output valid using macrocell register preset/clear (note 2 ) 70 ns t avwl t slwl t whdx t whax t wlwh t dvwh address valid data valid address non-multiplexed bus data non-multiplexed bus csi wr ai04909
55/63 dsm2180f3v table 33. flash memory program, write and erase times note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. table 34. reset (reset ) timing note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. figure 36. reset (reset ) timing symbol parameter min. typ. max. unit flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 5 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns symbol parameter conditions min max unit t nlnh reset active low time 1 300 ns t nlnhCpo power on reset active low time 1 ms t opr reset high to operational device 300 ns t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
dsm2180f3v 56/63 table 35. isc timing note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. figure 37. isc timing symbol parameter conditions -15 unit min max t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 10 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 45 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 45 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 2 mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 ns t iscpsu isc port set up time 13 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 36 ns t iscpzv isc port high-impedance to valid output 36 ns t iscpvz isc port valid output to high-impedance 36 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865
57/63 dsm2180f3v package mechanical plcc52 C 52 lead plastic leaded chip carrier, rectangular note: drawing is not to scale. plcc52 C 52 lead plastic leaded chip carrier, rectangular symbol mm inches typ. min. max. typ. min. max. a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 C 0.91 C 0.036 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.261 0.0097 0.0103 d 19.94 20.19 0.785 0.795 d1 19.05 19.15 0.750 0.754 d2 17.53 18.54 0.690 0.730 e 19.94 20.19 0.785 0.795 e1 19.05 19.15 0.750 0.754 e2 17.53 18.54 0.690 0.730 e 1.27 C C 0.050 C C r 0.89 C C 0.035 C C n52 52 nd 13 13 ne 13 13 plcc-b d e1 e 1 n d1 cp b d2/e2 e b1 a1 a a2 d3/e3 m l1 l c m1
dsm2180f3v 58/63 table 36. a ssignments C plcc52 pin no. pin assignments pin no. pin assignments 1 gnd 27 pa2 2 pb5 28 pa1 3 pb4 29 pa0 4 pb3 30 ad0 5 pb2 31 ad1 6 pb1 32 ad2 7 pb0 33 ad3 8 pd2 34 ad4 9 pd1 35 ad5 10 pd0 36 ad6 11 pc7 37 ad7 12 pc6 38 v cc 13 pc5 39 ad8 14 pc4 40 ad9 15 v cc 41 ad10 16 gnd 42 ad11 17 pc3 43 ad12 18 pc2 (vstby) 44 ad13 19 pc1 45 ad14 20 pc0 46 ad15 21 pa7 47 cntl0 22 pa6 48 reset 23 pa5 49 cntl2 24 pa4 50 cntl1 25 pa3 51 pb7 26 gnd 52 pb6
59/63 dsm2180f3v pqfp52 - 52 lead plastic quad flatpack note: drawing is not to scale. pqfp52 - 52 lead plastic quad flatpack symb. mm inches typ. min. max. typ. min. max. a 2.35 0.093 a1 0.25 0.010 a2 2.00 1.80 2.10 0.079 0.077 0.083 b 0.22 0.38 0.009 0.015 c 0.11 0.23 0.004 0.009 d 13.20 12.95 13.45 0.520 0.510 0.530 d1 10.00 9.90 10.10 0.394 0.390 0.398 d2 7.80 C C 0.307 C C e 13.20 12.95 13.45 0.520 0.510 0.530 e1 10.00 9.90 10.10 0.394 0.390 0.398 e2 7.80 C C 0.307 C C e 0.65 C C 0.026 l 0.88 0.73 1.03 0.035 0.029 0.041 l1 1.60 C C 0.063 a 0 7 0 7 n52 52 nd 13 13 ne 13 13 cp 0.10 0.004 qfp nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 l1
dsm2180f3v 60/63 table 37. p in assignments C pqfp52 pin no. pin assignments pin no. pin assignments 1 pd2 27 ad4 2 pd1 28 ad5 3 pd0 29 ad6 4 pc7 30 ad7 5pc6 31 v cc 6 pc5 32 ad8 7 pc4 33 ad9 8 v cc 34 ad10 9 gnd 35 ad11 10 pc3 36 ad12 11 pc2 37 ad13 12 pc1 38 ad14 13 pc0 39 ad15 14 pa7 40 cntl0 15 pa6 41 reset 16 pa5 42 cntl2 17 pa4 43 cntl1 18 pa3 44 pb7 19 gnd 45 pb6 20 pa2 46 gnd 21 pa1 47 pb5 22 pa0 48 pb4 23 ad0 49 pb3 24 ad1 50 pb2 25 ad2 51 pb1 26 ad3 52 pb0
61/63 dsm2180f3v part numbering table 38. ordering information scheme note: 1. the 5v10% devices are not covered by this data sheet, but by the dsm2180f3 data sheet. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: dsm21 80 f3 v - 15 t 6 device type dsm21 = dsp system memory for adsp-21xx family dsp applicability 80 = analog devices adsp-218x family memory density f3 = 1 mbit x 8 (128k bytes) operating voltage (vcc) blank 1 = 5v 10% v = 3.3v 10% access time 90 = 90 nsec 15 = 150 nsec package k = 52-pin plcc t = 52-pin pqfp temperature range 6 = C40 to 85 o c (industrial)
dsm2180f3v 62/63 revision history table 39. document revision history date rev. description of revision 06-nov-2001 1.0 document for the 3.3v10% range separated out from the data sheet on the 5v10% range 17-dec-2001 1.1 pqfp52 package mechanical data updated
63/63 dsm2180f3v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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